1. Field of the Invention
The present invention relates to a logic circuit and, more particularly, to a logic circuit having a high operating speed.
2. Description of the Prior Art
With the recent development of the advanced information-oriented society, a semiconductor integrated circuit device of high speed, high integration and low power consumption is increasingly demanded. Especially, electronic devices using compound semiconductors in III to V groups such as GaAs instead of conventional silicon have been energetically studied and developed to satisfy this demand.
As examples of transistors using GaAs, an MESFET (Metal Semiconductor Junction Field Effect Transistor), an HEMT (High Electron Mobility Transistor), an HBT (Hetero Junction Bipolar Transistor), an RHET (Resonant Hot Electron Transistor) and the like are proposed. Since the HEMT, HBT and RHET need advanced processing techniques, such as epitaxial growth by MBE Molecular Beam Epitaxy), MO-CVD (Metal Organic-Chemical Vapor Deposition) and the like, it will take some time to use them practically. On the other hand, as for the MESFET, a 16 K S RAM, a 3 KG gate array and the like are disclosed, and a product integrated on an LSI level is now at the beginning of its practical use.
Logic circuits using GaAs MESFET, which have been proposed, are for example circuits of DCFL (Direct Coupled FET Logic), BFL (Buffered FET Logic), SCFL (Source coupled FET Logic , LPFL (Low Pinchoff-Voltage FET Logic), and SDFL (Schottky-Diode FET Logic).
FIG. 1 is a schematic diagram showing one example of a conventional DCFL circuit. Referring to FIG. 1, the DCFL circuit comprises inverters 10 and 11 in two stages connected between a power supply V.sub.DD and the ground GND. The inverter 10 of the first stage comprises a load transistor 1 formed by a depletion MESFET and a drive transistor 2 formed by an enhancement MESFET, those transistors 1 and 2 being connected in series. The drain of the transistor 1 is connected to the power supply V.sub.DD The gate and source of the transistor 1 and the drain of the transistor 2 are connected together to constitute an output of the inverter 10. The source of the transistor 2 is connected to the ground. The gate of the transistor 2 is connected to an input terminal 100. The inverter 11 of the second stage comprises a load transistor 7 formed by a depletion MESFET and a drive transistor 8 formed by an enhancement MESFET, those transistors 7 and 8 being connected in series. The drain of the transistor 7 is connected to the power supply V.sub.DD. The gate and source of the transistor 7 and the drain of the transistor 8 are connected together to constitute an output of the inverter 11. The source of the transistor 8 is connected to the ground GND. The gate of the transistor 8 is connected to the output of the inverter 10. The output of the inverter 11 is connected to an output terminal 200 of this DCFL circuit.
The DCFL circuit comprises a few elements which are simply connected. Since the DCFL circuit operates at the highest speed with less power consumption among now proposed circuits, it has been employed in a memory device and many other LSI's. On the other hand, however, the DCFL circuit has a defect that a high level of output V.sub.OH at the first stage is limited below a clamp voltage of the transistor at the second stage. More specifically, referring to FIG. 1, the output voltage of the inverter 10 of the first stage is limited by the clamp voltage between the gate and source of the drive transistor 8 of the inverter 11 of the second stage. In general, the high-level output V.sub.OH of the inverter 10 is limited below 0.6 V because the clamp voltage between the gate and source of the MESFET is approximately 0.6 V. A low level of output V.sub.OL is approximately 0.1 V. Therefore, the output of the inverter has a logic amplitude V.sub.L of approximately 0.5 V. An ECL (Emitter Coupled Logic) circuit employing a silicon bipolar transistor operates within the range of the logic amplitude of approximately 0.5 V because the logic level is determined, using a well-controllable base-emitter voltage V.sub.BE or resistance ratio. In the case of the DCFL circuit employing the MESFET, since the logical level is affected by variable parameters such as, for example, a threshold voltage V.sub.TH and current characteristics, it is very difficult to assure a sufficient noise margin with the logic amplitude of approximately 0.5 V and to mass-produce a large scale integrated circuit. A BFL circuit shifts a level of an output voltage by a source follower provided at the output stage to obtain a large logic amplitude.
FIG. 2 is a schematic diagram showing one example of a conventional BFL circuit. Referring to FIG. 2, the BFL circuit comprises a logic branch 30 at a first stage and a source follower circuit 31 at a second stage 31. The logic branch 30 comprises a load transistor 9 formed by a depletion MESFET and a drive transistor 12 formed by a depletion MESFET, those transistors 9 and 12 being connected in series between a first power supply V.sub.DD and the ground GND. The drain of the transistor 9 is connected to the power supply V.sub.DD. The gate and source of the transistor 9 and the drain of the transistor 12 are connected together to constitute an output of the logic branch 30. The source of the transistor 12 is connected to the ground GND. The gate of the transistor 12 is connected to an input terminal 100. The source follower circuit 31 comprises a source follower transistor 20 formed by a depletion MESFET, a level shift diode 21 and a constant-current source transistor 22 formed by a depletion MESFET, which are connected in series between the power supply V.sub.DD and a power supply V.sub.SS. The transistor 20 has its drain connected to the power supply V.sub.DD, its source connected to an anode of the level shift diode 21 and its gate connected to the output of the logic branch 30. The drain of the transistor 22 is connected to a cathode of the diode 21 to constitute an output of the source follower circuit 31. The transistor 22 has its gate and its source connected together to the power supply V.sub.SS. The output of the source follower circuit 31 is connected to an output terminal 200.
Since the logic amplitude V.sub.L can be appropriately set by changing the number of the level shift diodes 21 in the source follower 31 in the BFL circuit shown in FIG. 2, the difficulty in manufacture caused by the small logic amplitude V.sub.L as in the DCFL circuit can be removed. On the other hand, in the BFL circuit, the level shifting performed in the output stage through which a large amount of current flows and the supply voltage of the level shift stage is high. Accordingly, power consumption of the BFL circuit is equal to or more than that of the ECL circuit of silicon.
FIG. 3 is a schematic diagram showing one example of a conventional SDFL circuit. In the SDFL circuit, the level shifting is performed in the input stage to reduce power consumption. The SDFL circuit in FIG. 3 is an NOR circuit having two inputs. Referring to FIG. 3, the SDFL circuit comprises an input-stage circuit and an output-stage circuit. The input-stage circuit comprises input level shift diodes 6a and 6b having anodes connected to input terminals 101 and 102, respectively for shifting the level of the input voltage and it further comprises an input pull-down transistor 4 formed by a depletion MESFET. The cathodes of the diodes 6a and 6b and the drain of the transistor 4 are connected together to constitute an output of the input stage circuit. The gate and source of the transistor 4 is connected together to a power supply V.sub.SS. The output-stage circuit comprises a load transistor 1 formed by a depletion MESFET, and a drive transistor 2 formed by an enhancement MESFET, which are connected in series between the power supply V.sub.DD and the ground GND. The drain of the transistor 1 is connected to the power supply V.sub.DD. The gate and source of the transistor 1 and the drain of the transistor 2 are connected together to constitute an output of the output stage circuit. The source of the transistor 2 is connected to the ground GND. The gate of the transistor 2 is connected to the output of the input stage circuit. The output of the output stage circuit is connected to an output terminal 200 of this SDFL circuit.
Description is now made as to operation of the SDFL circuit shown in FIG. 3.
The levels of the input voltages applied to the input terminals 101 and 102 are shifted by the input level shift diodes 6a and 6b, respectively, and applied to the gate of the drive transistor 2. The input pull-down transistor 4 functions as a constant-current source for supplying a substantially constant current flow into the input level shift diodes 6a and 6b. Assuming that the voltages, the levels of which are shifted by the input level shift diodes 6a and 6b, are approximately 0.6 V, the levels of the input voltages are shifted by approximately 0.6 V because the diodes 6a and 6b are provided in the input terminals 101 and 102, respectively. When a high-level voltage is applied from the input terminals 101 and 102 to the gate of the drive transistor 2 through the diode 6a or 6b, the logical level of the gate is clamped at approximately 0.6 V which is a clamp voltage between the source and the gate in the same manner as in the case of the DCFL circuit. On the other hand, when a low-level voltage, for example, 0.1 V is applied to the input terminal 101 and 102, the voltage of the gate of the transistor 2 is brought to -0.5 V by the level shifting of 0.6 V. Therefore, the logic amplitude V.sub.L of 1.1 V is provided and it is more than two times as large as the logic amplitude of 0.5 V in the DCFL circuit. Thus, the circuit is hardly affected by the change of the device parameter such as the threshold voltage V.sub.TH. In addition, since the level shifting is performed in the input stage in this SDFL circuit, a current flowing through the level shifting portion is small and power consumption is less than that of the BFL circuit. Although the enhancement MESFET is shown as the drive transistor 2 in FIG. 3, the depletion MESFET may be used for that.
FIG. 4 is a schematic diagram showing one example of a conventional LPFL circuit. The LPFL circuit in FIG. 4 is an NOR circuit having two inputs. Referring to FIG. 4, the gate and source of the input pull-down transistor 4 in the input stage are connected together to the ground GND compared with the SDFL circuit in FIG. 3. Other portions of the circuit are the same as that of the SDFL circuit shown in FIG. 3 and therefore description thereof is omitted.
Since in this LPFL circuit, the portion of the input level shift circuit in the input stage is not connected to the power supply V.sub.SS as in the SDFL circuit but is connected to the ground GND, there is an advantage that only one power supply is needed. However, it has a defect that the logic amplitude of the input voltage applied to the gate of the drive transistor 2 is reduced while the logic amplitude applied to the input terminal 101 or 102 is large. However, since the input voltage having the larger logic amplitude than that in the case of the DCFL circuit is applied to the LPFL circuit, the LPFL circuit is hardly affected by the noise from outside. When the voltage of a low level is applied to the gate of the transistor 2, the gate of the transistor 2 is brought to approximately 0V by the operation of the input pull-down transistor 4 and, as a result, the LPFL circuit allows a margin of approximately 100 mV for the logic amplitude as compared with the DCFL circuit.
The conventional SDFL circuit has the following disadvantages. Referring to FIG. 3, when the input voltage is changed from the high level to the low level, it is necessary to immediately discharge a capacitance C.sub.GS between the gate and the source of the drive transistor 2. In addition, when the input voltage is changed from the low level to the high level, it is necessary to immediately charge the gate capacitance C.sub.GS of the transistor 2. In order to promptly charge and discharge the gate capacitance C.sub.GS of the transistor 2, it is necessary to increase a channel width of the input pull-down transistor 4. However, the increase in the channel width of the transistor 4 causes a decrease in the fan-out of the logic circuit of the first stage connected to the input terminal 101 and 102 because a current flowing into the level shifting portion of the input in the input-stage circuit is applied from the load transistor of the logic circuit of the first stage and it is necessary to increase power capacity of the circuit of the first stage.
As described above, the two requirements, that is, a higher operating speed in the SDFL circuit shown in FIG. 3, and an increase in the fan-out of the circuit of the first stage can not be satisfied at the same time.
The prior art of interest to a logic circuit in accordance with the present invention is disclosed in a paper "A 64 K GaAs Gate Array" by Toshiyuki Terada et al., in ISSCC (International Solid-State Circuits Conference) of IEEE held Feb, 26, 1987. This paper states that both high-speed operation and a wide noise margin in a logic circuit can be brought about because input level shift diodes can operate as feedforward capacitance.
Another prior art of interest to the logic circuit in accordance with the present invention is disclosed in a paper "GaAs Gate Array Designs Using the Capacitor Diode FET Logic (CDFL) Approach" presented by F. S. Lee et al., in Custom Integrated Circuits Conference of IEEE held in 1986. This paper states that high speed operation of a logic circuit can be attained by connecting input level shift diodes to a feedforward capacitance in parallel.
Still other prior art of interest to the logic circuit in accordance with the present invention is disclosed in a paper, "The Design and Performance of a GaAs 2 K Gate Array" presented by Andrzej Peczalski et al., in Custom Integrated Circuits Conference of IEEE held in 1986. This paper describes the bootstrap SDFL circuit in which a series connection of two diodes is connected to a pull-up transistor in parallel in order to increase load driving ability.